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KTek Resourcing

, , Canada / Global

Senior Design Verification Engineer

Job Description

Mandate Skills: Design verification engineers with UVM experience

ASIC Programs (Switch/NIC) DV Lead or contribute to verification of 4–5 ASIC design blocks.

Develop UVM-based verification environments, sequences, tests, debug, and coverage closure.

Strong experience in SystemVerilog/UVM.

Ability to independently own verification deliverables.

Support customer collaboration in EST timezone.

Required Skills Ability to own design blocks independently and drive verification closure

Responsibilities The DV team is expected to: Own verification of 4–5 design blocks per ASIC

Develop and execute sequences

Perform test development and debug

Drive coverage collection and closure

Own end-to-end verification execution for assigned blocks

The customer will own the testbench infrastructure.

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